The present invention relates to integrated circuits and semiconductor device fabrication and, more specifically, to interconnect structures and methods of fabricating an interconnect structure.
A back-end-of-line (BEOL) interconnect structure may be used to connect device structures fabricated on a substrate during front-end-of-line (FEOL) processing with each other and with the environment external to the chip. Self-aligned patterning processes used to form a BEOL interconnect structure involve mandrels as sacrificial features that establish a feature pitch. Sidewall spacers, which have a smaller thickness than permitted by the current ground rules for optical lithography, are formed adjacent to the vertical sidewalls of the mandrels. After selective removal of the mandrels, the sidewall spacers are used as an etch mask to etch an underlying hardmask, for example, with a directional reactive ion etch (RIE) process. Unmasked features in the pattern are transferred from the hardmask to a dielectric layer to define trenches in which the wires of the BEOL interconnect structure are formed.
Cuts may be formed in mandrels with a cut mask and etching in order to section the mandrels and define gaps that may be subsequently used to produce wires that are spaced apart at their tips with a tip-to-tip spacing. A pattern reflecting the cut mandrels may be transferred to the hardmask and subsequently from the hardmask to the patterned interlayer dielectric layer. Non-mandrel cuts may also be formed in the hardmask itself and define gaps that may be filled by dielectric material when the sidewall spacers are formed. The filled gaps may be subsequently used to produce wires in the patterned interlayer dielectric layer that are spaced apart at their tips with a tip-to-tip spacing.
Improved interconnect structures and methods of fabricating an interconnect structure are needed.